Method of manufacturing semiconductor device and semiconductor device
US6962870B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2004 |
| Grant date | Nov 8, 2005 |
| Priority date | — |
| Expiry date | Jan 15, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor device comprising forming a protective film on a surface of a lower-layer interconnection, and forming a multilayer-structured film by stacking a first porous film, a first non-porous film, a second porous film, and a second non-porous film on a surface of the protective film in this order, and forming a via hole and an interconnect trench. After a resist mask is removed, protective film exposed at a bottom of the via hole is removed. An upper-layer interconnection of dual damascene structure is formed by embedding an interconnect material in the via hole and the interconnect trench.The first non-porous film includes a first layer has a high etching selectivity ratio relative to the protective film, and a second layer has a high etching selectivity ratio relative to the resist mask and the second porous film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.