Method for forming a low-k dielectric layer for a semiconductor device
US6962876B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 2004 |
| Grant date | Nov 8, 2005 |
| Priority date | — |
| Expiry date | Nov 5, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3211
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a low-k dielectric layer for a semiconductor device using an ALD process including (a) forming predetermined interconnection patterns on a semiconductor substrate, (b) supplying a first and a second reactive material to a chamber having the substrate therein, thereby adsorbing the first and second reactive materials on a surface of the substrate, (c) supplying a first gas to the chamber to purge the first and second reactive materials that remain unreacted, (d) supplying a third reactive material to the chamber, thereby causing a reaction between the first and second materials and the third reactive material to form a monolayer, (e) supplying a second gas to the chamber to purge the third reactive material that remains unreacted in the chamber and a byproduct; and (f) repeating (b) through (e) a predetermined number of times to form a SiBN ternary layer having a predetermined thickness on the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.