Sublithographic nanoscale memory architecture
US6963077B2 · kind B2 · utility
43Cited by
4References
49Claims
0Family size
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Key dates
| Filing date | Jul 24, 2003 |
| Grant date | Nov 8, 2005 |
| Priority date | — |
| Expiry date | Jul 24, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/943
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array comprising nanoscale wires is disclosed. The nanoscale wires are addressed by means of controllable regions axially and/or radially distributed along the nanoscale wires. In a one-dimensional embodiment, memory locations are defined by crossing points between nanoscale wires and microscale wires. In a two-dimensional embodiment, memory locations are defined by crossing points between perpendicular nanoscale wires. In a three-dimensional embodiment, memory locations are defined by crossing points between nanoscale wires located in different vertical layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.