Methods and circuitry for implementing first-in first-out structure
US6963220B2 · kind B2 · utility
7Cited by
14References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2003 |
| Grant date | Nov 8, 2005 |
| Priority date | — |
| Expiry date | Dec 31, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2205/106
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.