Method and apparatus for generating and controlling a quadrature clock
US6963236B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2003 |
| Grant date | Nov 8, 2005 |
| Priority date | — |
| Expiry date | Dec 10, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00286
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Quadrature clock generating apparatus includes a multiplexer selecting one of a generated clock and a gated generated clock as a double clock in accordance with a halt multiplexer control. Divider circuitry provides an alignment signal corresponding to an inverted double clock divided by two. A recovery circuit recovers first and second clocks having a 90° phase difference from the double clock in accordance with the alignment signal. A halt circuit controls the halt multiplexer control to select the gated generated clock when the alignment signal matches a pre-determined clock level. The halt multiplexer control is clocked by the generated clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.