Image processing apparatus
US6963420B1 · kind B1 · utility
5Cited by
6References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2000 |
| Grant date | Nov 8, 2005 |
| Priority date | — |
| Expiry date | May 4, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N1/0083
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The image processing apparatus comprises an input I/F memory which reads pixels having a predetermined length, subjects the read pixels to buffering, and writes them in a SIMD type processor. The SIMD type processor performs batch processing of the pixels. Further, an output I/F memory reads the pixels batch-processed by the SIMD type processor, subjects the read pixels to buffering and writes them in a predetermined output destination. Read and/or write timing of IN—FIFO and OUT—FIFO is appropriately controlled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.