Floating point pipeline method and circuit for fast inverse square root calculations
US6963895B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 1, 2000 |
| Grant date | Nov 8, 2005 |
| Priority date | — |
| Expiry date | May 1, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems are provided for fast computation of reciprocal square root for floating-point numbers. A piece-wise linear approximation of the result mantissa is computed in two cycles and used as the input to an iteration sequence that converges cubically. Three iterations produce a result with accuracy sufficient for computer graphic applications. The initial estimate and input operand are scaled to minimize final adjustments to the result mantissa and final exponent adjustments required by the algorithm are performed concurrently with any adjustment required by rounding. A pipelined implementation of the algorithm produces a result with a latency of 24 and a repeat rate of 21 clock cycles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.