Clock generation for multiple secondary buses of a PCI bridge
US6963990B2 · kind B2 · utility
7Cited by
8References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 5, 2002 |
| Grant date | Nov 8, 2005 |
| Priority date | — |
| Expiry date | Sep 10, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments are provided in which clock generation for a PCI bridge and its N attached secondary buses is carried out by using an external PLL clock generator which generates N+1 first clock signals at a first frequency to the bridge and to N multiplexers. The bridge in turn generates N second clock signals to the N multiplexers. Each of the N clock signals generated by the bridge can be at either a second or third frequency. Each of the N multiplexers passes one of the first clock signal and second clock signal to a secondary bus depending on the speed of the slowest adapter on the secondary bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.