Synchronizing and aligning differing clock domains
US6963991B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2002 |
| Grant date | Nov 8, 2005 |
| Priority date | — |
| Expiry date | Oct 11, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention relate to a memory control hub (MCH) clock master of an MCH. Typically, in a computer system, a processor is coupled to the MCH by a front-side bus (FSB). Further, an input/output control hub (ICH) is typically coupled to the MCH by a back-side bus or Hub Link. In one embodiment, a host phase locked loop (HPLL) of the MCH clock master receives an FSB clock signal transmitted on the FSB and generates a local synchronous clock signal based upon the FSB clock signal. A delayed lock loop (DLL) of the MCH clock master also receives the FSB clock signal and generates a system clock signal. Particularly, the DLL synchronizes the system clock signal to the local synchronous clock and drives the system clock signal to many different devices on the board.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.