Method and apparatus for testing a system-on-a-chip
US6964004B2 · kind B2 · utility
3Cited by
7References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2002 |
| Grant date | Nov 8, 2005 |
| Priority date | — |
| Expiry date | Dec 3, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3167
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for testing a system on a chip or a system on a package (““SOPC”) having a plurality of internal modules that are tested to determine whether predetermined performance specifications are satisfied. A first module of the SOPC is selected for testing. A determination is made as to whether the first module is directly accessible or not. If the first module is directly accessible, the module may be tested with automated test equipment external to the SOPC. If the first module is not directly accessible, the module may be tested with a second and third module of the SOPC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.