LED power package
US6964877B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2004 |
| Grant date | Nov 15, 2005 |
| Priority date | — |
| Expiry date | Apr 27, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/8585
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Surface mount light emitting diode (LED) packages each contain a light emitting diode (LED) die (24). A plurality of arrays of openings are drilled into an electrically insulating sub-mount wafer (10). A metal is applied to the drilled openings to produce a plurality of via arrays (12). The LED dice (24) are flip-chip bonded onto a frontside (16) of the sub-mount wafer (10). The p-type and n-type contacts of each flip-chip bonded LED (24) electrically communicate with a solderable backside (18) of the sub-mount wafer (10) through a via array (12). A thermal conduction path (10, 12) is provided for thermally conducting heat from the flip-chip bonded LED dice (24) to the solderable backside (18) of the sub-mount wafer (10). Subsequent to the flip-chip bonding, the sub-mount wafer (10) is separated to produce the surface mount LED packages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.