Laminated chip electronic device and method of manufacturing the same
US6965167B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 17, 2003 |
| Grant date | Nov 15, 2005 |
| Priority date | — |
| Expiry date | Dec 5, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01G4/232
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a laminated chip electronic device and a method of manufacturing the same. In the laminated chip electronic device and the method of manufacturing the same according to the present invention, a body is made of a non-linear resistance coefficient material and has a plurality of conductive layers formed therein; an insulating layer is formed on the top, bottom, front and back surfaces of the body; and two electrodes are formed at the two ends of the body and electrically connected to the terminals of the conductive layers, respectively. Furthermore, in the present invention, two soldered interface layers are formed on the two electrodes, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.