Input buffer with hysteresis option
US6965251B1 · kind B1 · utility
9Cited by
31References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2004 |
| Grant date | Nov 15, 2005 |
| Priority date | — |
| Expiry date | Mar 10, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018585
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The invention provides a high-speed buffer that may used at the input of an integrated circuit, such as an input buffer. This buffer may be configured for use as a standard buffer with a single switching threshold, such as a TTL-to-CMOS buffer, or used as a Schmitt trigger with hysteresis, which as at least two switching thresholds. The integrated circuit may be a programmable logic device (PLD) or field programmable gate array (FPGA), but in other embodiments, the integrated circuit may be other types of devices such a microprocessors, ASICs, or memories.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.