Reduced-capacitance bus switch in isolated P-well shorted to source and drain during switching
US6965253B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2004 |
| Grant date | Nov 15, 2005 |
| Priority date | — |
| Expiry date | Jul 9, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/162
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A bus switch has reduced input capacitance. Parasitic source-to-well and drain-to-well capacitors are shorted by well-shorting transistors, eliminating these parasitic capacitances. The well-shorting transistors are turned on when the bus-switch transistor is turned on, but are turned off when the bus-switch transistor is turned off and the bus switch isolates signals on its source and drain. The isolated P-well under the bus-switch transistor and the well-shorting transistors is not tied to ground. Instead the isolated P-well is floating when the bus-switch transistor is turned on. When the bus-switch transistor is turned off, the underlying isolated P-well is driven to ground by a biasing transistor in another P-well. Since the isolated P-well has a much lower doping than the N+ source and drain, the capacitance of the well-to-substrate junction is much less than the source-to-well capacitance. Thus input capacitance is reduced, allowing higher frequency switching.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.