Bipolar differential input stage with input bias current cancellation circuit
US6965267B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2004 |
| Grant date | Nov 15, 2005 |
| Priority date | — |
| Expiry date | Apr 28, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45576
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A bipolar differential input stage with an input bias current cancellation circuit comprises an input pair and a bipolar tracking transistor. The input stage is arranged such that the collector currents in the input pair and tracking transistor, and the collector-emitter voltages of the input pair and tracking transistor, are substantially equal. A lateral PNP transistor's first collector provides the tracking transistor base current required to achieve the substantially equal collector current, and second and third collectors provide copies of the tracking transistor base current as bias current cancellation currents to the bases of the input pair, thereby reducing the input stages' input bias currents.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.