Memory device having high bus efficiency of network, operating method of the same, and memory system including the same
US6965528B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 14, 2003 |
| Grant date | Nov 15, 2005 |
| Priority date | — |
| Expiry date | Jan 12, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/229
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device having a high bus efficiency on a network, an operating method of the memory device, and a memory system including the memory device are provided. The memory device includes banks, a programming register, and a controller. Each of the banks has a plurality of memory cells arranged in a matrix of rows and columns. In a write operation, the programming register stores simultaneous write information on how many banks there are in which data are stored. In a read operation, the controller selects one of the banks subjected to the write operation in response to the simultaneous write information to read out the memory cell data in the selected bank.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.