Semiconductor memory device having a reference cell
US6965531B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 16, 2003 |
| Grant date | Nov 15, 2005 |
| Priority date | — |
| Expiry date | Jun 16, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4099
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An open-bit semiconductor memory device includes a plurality of memory cell arrays, wherein half of the memory cells in the memory cell array and half of the memory cells in the adjacent memory cell array store therein complementary data. The memory device further includes a pair of reference cell arrays sandwiching therebetween the memory cell arrays for supplying reference data for reading data from the memory cells in the adjacent memory cells. The reference cell array includes a plurality reference bit lines each connected to reference cells in number smaller than the number of memory cells connected to the bit line, and yet has a resistance and a capacitance equivalent to the resistance and the capacitance of the bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.