Packet striping across a parallel header processor
US6965615B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2000 |
| Grant date | Nov 15, 2005 |
| Priority date | — |
| Expiry date | Jan 2, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/3063
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A technique is provided for striping packets across pipelines of a processing engine within a network switch. The processing engine comprises a plurality of processors arrayed as pipeline rows and columns embedded between input and output buffers of the engine. Each pipeline row or cluster includes a context memory having a plurality of window buffers of a defined size. Each packet is apportioned into fixed-sized contexts corresponding to the defined window size associated with each buffer of the context memory. The technique includes a mapping mechanism for correlating each context with a relative position within the packet, i.e., the beginning, middle and end contexts of a packet. The mapping mechanism facilitates reassembly of the packet at the output buffer, while obviating any any out-of-order issues involving the particular contexts of a packet.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.