System and method for block error correction in packet-based digital communications
US6965636B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2000 |
| Grant date | Nov 15, 2005 |
| Priority date | — |
| Expiry date | Jul 4, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2001/0093
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system and method for efficiently correcting block errors in packet-based digital communications are provided whereby the ratio of redundant symbols/message symbols over the length of a data packet decreases in order to more efficiently use available bandwidth. The reduction of this ratio, and subsequently the change in a corresponding framing schedule, may be determined through negotiations between the transmitting device and the receiving devices. Each receiving device calculates a redundancy requirement based on signal-to-noise ratio samples. This requirement is returned to the transmitting device in the form of a schedule request. The transmitting device determines if a new framing schedule is needed based on the schedule request, and communicates this new framing schedule to the receiving device. Once the receiving device acknowledges receipt of the new schedule, the transmitting device switches to the new framing schedule for future data packet transmissions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.