Method of using transient faults to verify the security of a cryptosystem
US6965673B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 1, 2000 |
| Grant date | Nov 15, 2005 |
| Priority date | — |
| Expiry date | Mar 1, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/7219
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A useful method of verifying the integrity of a cryptosystem involves using erroneous outputs to obtain secret information. In certain signature schemes which use the Chinese Remainder Theorem, a correct signature of a message and an erroneous signature of the same message permit the modulus to be easily obtained. If the content of the message is known, such cryptosystems may be cracked with only an erroneous signature of the message. Certain other authorization schemes may be cracked by analyzing a number of erroneous outputs caused by a particular type of error called a “register fault.” A security expert or cryptosystem designer may intentionally induce a tamper proof device generate a faulty computation by subjecting the device, such as a smart card, to physical stress, such as certain types of radiation, atypical voltage levels, or a higher clock rate than the device was designed to accommodate. Cryptosystems should be impervious to the attacks described herein. If not, the system should be modified or discarded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.