Non-uniform cache apparatus, systems, and methods
US6965969B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 8, 2004 |
| Grant date | Nov 15, 2005 |
| Priority date | — |
| Expiry date | Oct 8, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/271
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus or system may comprises cache control circuitry coupled to a processor, and a plurality of independently accessible memory banks (228) coupled to the cache control circuitry. Some of the banks may have non-uniform latencies, organized into two or more spread bank sets (246). A method may include accessing data in the banks, wherein selected banks are closer to the cache control circuitry and/or processor than others, and migrating a first datum (445) to a closer bank from a further bank upon determining that the first datum is accessed more frequently than a second datum, which may be migrated to the further bank (451).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.