Multi-sequence burst accessing for SDRAM
US6965980B2 · kind B2 · utility
Assignees
Inventor
Key dates
| Filing date | Feb 14, 2002 |
| Grant date | Nov 15, 2005 |
| Priority date | — |
| Expiry date | Jul 13, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for accessing memory locations in a memory device in different orders. In one implementation, a memory device includes: a memory array, including a plurality of memory locations divided into memory pages, where each memory location has a row address and a column address; a row decoder connected to the memory array for selecting a row address in the memory array; a column decoder connected to the memory array for selecting a column address in the memory array; and a multi-sequence address generator for generating addresses, where the multi-sequence address generator has a burst mode and in burst mode generates one of two or more burst sequences of addresses according to received burst parameters, and where each sequence has an index indicating the separation between two addresses in the sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.