Simultaneously setting prefetch address and fetch address pipelined stages upon branch
US6965983B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 16, 2003 |
| Grant date | Nov 15, 2005 |
| Priority date | — |
| Expiry date | Feb 26, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3804
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pipelined CPU includes a pre-fetch (PF) stage for performing branch prediction, and an instruction fetch (IF) stage for fetching instructions that are to be later processed by an execution (EX) stage. The PF stage has a PF address (PFA) register for storing the address of an instruction being processed by the PF stage, and the IF stage has an IF address (IFA) register for storing the address of an instruction to be fetched for later execution. The CPU also includes address register control (ARC) circuitry for setting the contents of the PFA and the IFA. The ARC accepts branch-prediction results from the PF stage to determine the subsequent contents of the PFA and the IFA. If the PF stage predicts a branch, then the ARC sets the next address of the PFA to be sequentially after a predicted branch address, and simultaneously sets the next address of the IFA to be the predicted branch address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.