Dynamic circuit
US6967502B2 · kind B2 · utility
1Cited by
5References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 11, 2003 |
| Grant date | Nov 22, 2005 |
| Priority date | — |
| Expiry date | Sep 22, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0963
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a dynamic circuit, when only between a precharge node and an intermediate node through a plurality of logical-operating MOS transistors is conducted, the potential of the precharge node approximately drops to High*{C1/(C1+C2)} from High, where C1represents the capacitance of the precharge node and C2 represents the capacitance of the intermediate node. Thereafter, with the charge from a power supply, the precharge node returns to High. At this charge sharing time, the amount of charge supply from the power supply is adjusted to suppress voltage drop of the precharge node, thereby reducing noise.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.