Circuit arrangement for the discrete-time comparison of signals
US6967506B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 17, 2002 |
| Grant date | Nov 22, 2005 |
| Priority date | — |
| Expiry date | Mar 5, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356139
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The invention pertains to a circuit arrangement (comparator) for the discrete-time comparison of input signals (ip, vrefp) and for making available a pair of complementary output levels (vdd, vss) which corresponds to the result of the comparison on a line pair (P, N), wherein said circuit arrangement comprises a reset circuit (12) for balancing the line potentials during a reset phase, an input circuit (14) for generating a potential difference on the line pair (P, N) in accordance with an input signal difference, a first bistable flip-flop (16) for amplifying the generated potential difference and a second bistable flip-flop (20) that is connected by means of a connecting circuit (18) and serves for additionally amplifying the generated potential difference to the desired complementary output levels.According to the invention, a third bistable flip-flop (30a, 30b) is provided that, when connecting the second flip-flop (20) parallel to the first flip-flop (16), amplifies the generated potential difference and thusly reduces the comparison time without significantly impairing the current consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.