Method and apparatus for digital duty cycle adjustment
US6967514B2 · kind B2 · utility
70Cited by
28References
78Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 21, 2002 |
| Grant date | Nov 22, 2005 |
| Priority date | — |
| Expiry date | Dec 7, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00208
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Adjusting a clock duty cycle. An incremental error signal is generated in response to the clock signal. A cumulative error signal is generated in response to the incremental error signal. The incremental error signal is reset and the duty cycle of the clock signal is adjusted in response to the cumulative error signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.