Sigma-delta analog-to-digital converter (ADC) with truncation error cancellation in a multi-bit feedback digital-to-analog converter (DAC)
US6967608B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2004 |
| Grant date | Nov 22, 2005 |
| Priority date | — |
| Expiry date | Jun 25, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/454
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for reducing the complexity of a multi-bit DAC in a sigma-delta ADC. The DAC resolution can be made to be less than that of the quantizer by canceling truncation error present in multi-bit DACs. Truncation errors are introduced by differences between the digital output word of the quantizer and the digital input word of the feedback DAC(s). The truncation error(s) can be cancelled and eliminated from the system transfer function. A preferred embodiment comprises expanding all feedback loops in the ADC, adding an adjusted truncation error for each feedback loop to an inner feedback loop, and then calculating a correction term for each adjusted truncation error. The correction term can be calculated by zeroing all signals except for the adjusted truncation error being canceled and then calculating a truncation error transfer function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.