System for reordering sequenced based packets in a switching network
US6967951B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 11, 2002 |
| Grant date | Nov 22, 2005 |
| Priority date | — |
| Expiry date | Apr 4, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/34
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
System for reordering sequenced based packets in a switching network. The system includes a plurality of source processors that transmit the packets to a destination processor via multiple communication fabrics. The source processors and the destination processor are synchronized together. Time stamp logic at each source processor operates to include a time stamp parameter with each of the packets transmitted from the source processors. The system also includes a plurality of memory queues located at the destination processor. An Enqueue processor operates to store a memory pointer and an associated time stamp parameter for each of the packets received at the destination processor in a selected memory queue. A Dequeue processor determines a selected memory pointer associated with a selected time stamp parameter and operates to process the selected memory pointer to access a selected packet for output in a reordered packet stream.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.