Circuit-level memory and combinational block modeling
US6968305B1 · kind B1 · utility
0Cited by
14References
51Claims
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Key dates
| Filing date | Jun 2, 2000 |
| Grant date | Nov 22, 2005 |
| Priority date | — |
| Expiry date | Nov 2, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for creating a memory model for use in modeling a physical memory of an electronic circuit design. Memory write operations to the physical memory and memory read operations are modeled in a lookup table. The number of entries in the lookup table is limited by an upper bound representing a total number of memory operations that can occur over a given number of clock cycles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.