User available body scan chain
US6968487B1 · kind B1 · utility
13Cited by
32References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2002 |
| Grant date | Nov 22, 2005 |
| Priority date | — |
| Expiry date | Apr 8, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17796
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of accessing the testing means in a Field Programmable Gate Array (“FPGA”) comprised of a plurality of functional groups (“FGs”) comprising: inputting a function netlist defining a user circuit; compiling said function netlist; and generating a logic Built-In Self Test (“BIST”) netlist; wherein said BIST netlist replaces all user registers with scan registers with a scan chain routed as the physical silicon scan chains.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.