Method and apparatus to optimize an integrated circuit design using transistor folding
US6968524B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2001 |
| Grant date | Nov 22, 2005 |
| Priority date | — |
| Expiry date | Apr 6, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system are disclosed to optimize an integrated circuit layout design by determining possible lengths of layout rows that will reduce the total area of the integrated circuit layout (FIG. 4B). The possible row lengths (401B) are determined and stored in a memory unit as a set of possible optimal row length values. A set of possible optimal row heights corresponding to the determined set of possible rowlengths is determined and the total chip area is iteratively calculated. Optimal values of rowlength and row height are chosen based upon the maximum chip area reduction. Once the optimal row length and height parameters are chosen, transistor devices placed in each row of the integrated circuit layout are folded to achieve the optimal row length and height.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.