Clocked cycle latch circuit
US6970018B2 · kind B2 · utility
3Cited by
11References
35Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2004 |
| Grant date | Nov 29, 2005 |
| Priority date | — |
| Expiry date | Jun 23, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356156
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A cycle latch includes a control circuit which increases the pull-up rate of a storage node by conditionally discharging the feedback node in a cross-coupled inverter keeper structure. The cycle latch includes an NMOS transistor switch for transferring an input value to the storage node, and two more NMOS transistors connected in series for performing the function of the control circuit. By connecting the storage node to a pre-discharged feedback node and then driving the latch with a low-swing clock, improved performance in terms of delay times, energy consumption, and robustness is achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.