Multiplexer circuit for converting parallel data into serial data at high speed and synchronizing the serial data with a clock signal
US6970116B2 · kind B2 · utility
8Cited by
12References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 13, 2003 |
| Grant date | Nov 29, 2005 |
| Priority date | — |
| Expiry date | Nov 13, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M9/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A multiplexer circuit converts parallel data into serial data synchronized with an internal clock signal, and the multiplexer circuit has a logic circuit, a load circuit, and a plurality of switching elements. The logic circuit processes the internal clock signal and the parallel data. The load circuit and the plurality of switching elements are connected in series between a first power source line and a second power source line. Each of the switching elements is controlled in accordance with an output of the logic circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.