Controlled frequency power factor correction circuit and method
US6970365B2 · kind B2 · utility
140Cited by
1References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 12, 2001 |
| Grant date | Nov 29, 2005 |
| Priority date | — |
| Expiry date | Jul 28, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A power factor correction (PFC) circuit (10) includes a latch (16) having an output that initiates a coil current (ICOIL) in response to a transition edge of a clock signal (CLOCK) to generate a PFC signal (VOUT). An input receives a control signal (TERM). A current modulation circuit (14) has a first input (36) coupled for receiving the PFC signal to establish a charging time (TCH) of the coil current. A second input senses the coil current to establish a duty cycle of the coil current over a period of the clock signal, and an output (38) provides the control signal as a function of the charging time and the duty cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.