Memory device
US6970369B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2002 |
| Grant date | Nov 29, 2005 |
| Priority date | — |
| Expiry date | Mar 18, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a memory device having a controller and multiple memory modules both of which are mounted together on a motherboard, a high-speed operation is executed by suppressing waveform distortion caused by signal reflection. Since signal reflection occurs when a controller performs the writing/reading of data relative to memory units on memory modules, active terminator units are included in the controller and the memory units. These active terminator units are provided for a data bus and/or a clock bus in order to terminate these buses in memory units. The active terminator units provided for the controller and the memory units may be put into an inactive state when data is to be received.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.