Methods of redundancy in a floating trap memory element based field programmable gate array
US6970383B1 · kind B1 · utility
48Cited by
7References
49Claims
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Key dates
| Filing date | Jun 10, 2003 |
| Grant date | Nov 29, 2005 |
| Priority date | — |
| Expiry date | Nov 2, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0441
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for providing redundancy in a floating charge trap device based programmable logic device includes the steps of sensing for a predetermined amount of stored charge in a first area of a floating trap devices in a floating trap device pair, and sensing for the predetermined amount of stored charge in a second area of the floating trap devices in the floating trap device pair when the charge in the stored charge in the first area in one of the floating trap devices is below the predetermined amount.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.