Programmable polarity for high speed differential interfaces
US6970516B1 · kind B1 · utility
1Cited by
4References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2001 |
| Grant date | Nov 29, 2005 |
| Priority date | — |
| Expiry date | Oct 24, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B3/36
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A system generally having a first circuit, a second circuit, and a pair of non-crossing conductive paths. The first circuit may be configured to convert between (i) a serial signal on a first differential interface and (ii) a parallel signal. The pair of non-crossing conductive paths may connect the first differential interface with a second differential interface. The second circuit may be configured to invert the parallel signal in response to a control signal in an inverting state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.