System for fast scrambling and descrambling of data
US6970563B1 · kind B1 · utility
2Cited by
5References
22Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 1, 2001 |
| Grant date | Nov 29, 2005 |
| Priority date | — |
| Expiry date | Nov 11, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03872
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method for parallel scrambling of a sequence of serially transmitted digital bits comprises an initializing scrambling step and subsequent scrambling step. The initializing scrambling step comprises the steps of generating a scrambling bit sequence and storing the scrambling bit sequence in a scrambling register. The subsequent scrambling step comprises:
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.