Method for initiating internal parity operations in a CAM device
US6971053B1 · kind B1 · utility
1Cited by
9References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 30, 2002 |
| Grant date | Nov 29, 2005 |
| Priority date | — |
| Expiry date | Jun 25, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit and a method of operating the circuit is provided. The method generally comprises the steps of (A) receiving an explicit error checking instruction generated outside the circuit, (B) performing an error checking operation for at least one of a plurality of memory locations within the circuit, and (C) generating a result signal from the error checking operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.