System and method for efficient convolutional interleaving/de-interleaving
US6971057B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2001 |
| Grant date | Nov 29, 2005 |
| Priority date | — |
| Expiry date | Jun 12, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/2732
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A memory optimized system and method for data interleaving/de-interleaving are disclosed. A data interleaver/de-interleaver may be implemented with a memory device and an improved data interleaver/de-interleaver. The improved data interleaver/de-interleaver may be implemented with a controller, a first array, and a second array. The first array identifies a maximum depth value for each of a plurality of memory segments responsive to both a block data length and the desired interleaving/de-interleaving depth. The second array comprises an index associated with each of the plurality of memory segments that may be used to derive write and read addresses. In its broadest terms, the method can be described as: identifying a block data length, N, and an interleaver/de-interleaver depth, D; initializing a set of pointers associated with each of N memory segments; initializing a set of pointer maximum values responsive to the relative magnitude of N and D, identifying a memory index responsive to a base address and the set of pointer maximum values; using a memory segment identifier, a word identifier, and a byte identifier along with the memory index and the pointers to write/read the byt…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.