Methods and apparatus for packaging integrated circuit devices
US6972480B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2003 |
| Grant date | Dec 6, 2005 |
| Priority date | — |
| Expiry date | Jun 20, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over the at least one chip scale packaging layer, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.