Optimization of error loops in distributed power amplifiers
US6972622B2 · kind B2 · utility
5Cited by
169References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 12, 2003 |
| Grant date | Dec 6, 2005 |
| Priority date | — |
| Expiry date | Jun 8, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/211
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Several feed-forward RF power amplifiers configured for use in a distributed array, each having a main amplifier within a carrier null loop and an error amplifier within an error loop. Each carrier null loop includes a switch configured to selectively disable the carrier null loop, thereby disabling the carrier null loop, and injecting an actual RF signal into the error loop allowing the error loop to be optimized using the actual RF signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.