Voltage detection circuit
US6972703B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2004 |
| Grant date | Dec 6, 2005 |
| Priority date | — |
| Expiry date | Dec 16, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/223
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A voltage detection circuit. A second NMOS transistor has a gate coupled to the gate of a first NMOS transistor. A comparator has input terminals, and an output terminal. A first resistor is coupled between the first input terminal and the source of the first NMOS transistor, a second resistor is coupled to the comparator and the first resistor, a third resistor is coupled between the second resistor and the comparator, and a fourth resistor is coupled between the second and third resistors, and ground. A first PMOS transistor has a gate coupled to the gates of the first and second NMOS transistors. A second PMOS transistor has a connected gate and drain, a source coupled to the gates of first and second NMOS transistors, a drain coupled to ground, and an n-well directly connected to the gates of the first and second NMOS transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.