Path AIS insertion for concatenated payloads across multiple processors
US6973041B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2000 |
| Grant date | Dec 6, 2005 |
| Priority date | — |
| Expiry date | Jul 19, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/40
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In a data transmission network, such as SONET, a method and apparatus for the generation of a path Alarm Insertion Signal (AIS) at the output of each of a number of concatenated pointer processors in response to a failure at the input of any one of the pointer processors. Each of the pointer processors has an input, an output and a bidirectional terminal that is coupled to a common node. Each of the pointer processors includes circuitry coupled to the input, the output and the bidirectional terminal that causes a predetermined logic level to be asserted at the bidirectional terminal in response to the appearance of an error signal at its input and that causes an AIS to appear at its output in response to either an error signal at its input or the assertion of the predetermined logic level at its bidirectional terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.