Reduced delay implementation of fourier transform based channelizers and de-channelizers
US6973135B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 5, 2000 |
| Grant date | Dec 6, 2005 |
| Priority date | — |
| Expiry date | Sep 22, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H17/0266
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a wireless telecommunications system, data processing delays associated with digital channelization and de-channelization may be reduced through the use of a technique that involves processing data blocks in conjunction with the transformation of the data blocks by a large, Fast Fourier Transform (FFT) algorithm, and makes use of multiple transmission and reception branches. In accordance with this technique, the processing delays associated with the FFT algorithm are minimized, but not to the detriment of other important channelizer/de-channelizer design characteristics, such as power consumption, die area and computational complexity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.