Digital-data receiver synchronization method and apparatus
US6973145B1 · kind B1 · utility
26Cited by
23References
10Claims
0Family size
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Key dates
| Filing date | Sep 1, 2000 |
| Grant date | Dec 6, 2005 |
| Priority date | — |
| Expiry date | Aug 6, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0685
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Digital-data receiver synchronization is provided with composite phase-frequency detectors, mutually cross-connected comparison feedback or both to provide robust reception of digital data signals. A single master clock may be used to provide frequency signals. Advantages can include fast lock-up time in moderately to severely noisy conditions, greater tolerance to noise and jitter when locked, and improved tolerance to clock asymmetries.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.