Techniques to adjust a signal sampling point
US6973147B2 · kind B2 · utility
2Cited by
14References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2002 |
| Grant date | Dec 6, 2005 |
| Priority date | — |
| Expiry date | Dec 19, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Techniques to adjust sampling times of an input signal. The techniques may utilize multi-level modification of the phase of a sampling clock. For example, the level of modification of the phase of the sampling clock may depend on the phase angle of the sampling clock in which transitions of the input signal occur.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.