Dynamic phase aligning interface
US6973151B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2001 |
| Grant date | Dec 6, 2005 |
| Priority date | — |
| Expiry date | Sep 18, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/02
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
According one embodiment, an apparatus and method are disclosed for a dynamic phase aligning input interface. In the embodiment, a first device provides data to a second device. According to the embodiment, the interface is counter clocked, the second device being clocked by a first clock signal and providing a second clock signal source to the first device for clocking the data. The first device transmits the second clock signal and the data to the second device, with the second clock signal being delayed by the period of time required for the second clock signal source to propagate through the first device. The second device detects the phase of the first clock signal and the second clock signal and modifies the phase of the second clock signal source to align the phase of the first clock signal and the phase of the second clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.