Multiprocessor write-into-cache system incorporating efficient access to a plurality of gatewords
US6973539B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2003 |
| Grant date | Dec 6, 2005 |
| Priority date | — |
| Expiry date | Jun 14, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0811
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiprocessor write-into-cache data processing system includes a feature for preventing hogging of ownership of a first gateword stored in the memory which governs access to a first common code/data set shared by processes running in the processors by imposing first delays on all other processors in the system while, at the same time, mitigating any adverse effect on performance of processors attempting to access a gateword other than the first gateword. This is achieved by starting a second delay in any processor which is seeking ownership of a gateword other than the first gateword and truncating the first delay in all such processors by subtracting the elapsed time indicated by the second delay from the elapsed time indicated by the first delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.