Scan insertion with bypass login in an IC design
US6973631B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 2003 |
| Grant date | Dec 6, 2005 |
| Priority date | — |
| Expiry date | May 9, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318555
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A computer implemented process of inserting enhanced scan bypass in relation to a bypassed block in an integrated circuit design comprising: receiving an HDL description of the circuit design; wherein the HDL description includes a port specification HDL instruction that specifies port properties of a bypassed block; wherein the HDL description includes an enhanced bypass HDL instruction that specifies how many scan cells to provide per port of the bypassed block in a scan bypass circuit that bypasses the bypassed block; wherein the bypass HDL instruction includes a user-selectable option of at least zero or one or two scan cells per port; in response to the specification HDL instruction and the enhanced bypass HDL instruction, automatically generating a netlist portion that includes scan a bypass circuit that bypasses the bypassed block and that includes the specified number of scan cells per port.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.